The present invention relates generally to the field of logic elements, and more particularly to the field of exclusive OR logic elements with pass gates forming reversing switches for use in selector and decision wait circuits.
Exclusive OR gates form an important part of asynchronous design. Asynchronous systems act on events occurring at unpredictable times, unlike a synchronous system having a clock determining when to execute an action. One frequently used method for encoding events in asynchronous systems is transition encoding. In transition encoding, any change in the level of a signal represents an event, whether the change is from false to true (i.e. low signal to high signal) or true to false (high to low). Thus, the asynchronous system reacts to changes in signal levels representing events to trigger an action or a response.
Asynchronous systems have long used selector circuits for transition encoding of events to initiate an action, but they need XOR gates to reset their inputs. As shown in FIG. 1, a selector circuit has one event input, A, two event outputs, B0 and B1, and one level input, C. When an event arrives at input A of the selector, the selector delivers an event to output B0 or B1. The Boolean value of input C selects which output gets the event. If C is true, the event appears at output B1. If C is false, the event appears at output B0.
FIG. 2 shows a well-known circuit representation for a selector circuit 200. Circuit 200 includes a pair of XOR gates, 210 and 220, and a pair of waiton gates, 230 and 240. Waiton gates 230 and 240 are essentially latches controlled by their side input. Each waiton gate passes the level at its input to its output if its side input is true. Therefore, waiton gate 230 passes the signal at its input if C is true. Waiton gate 240 passes the signal at its input if C is false because the side input of waiton gate 240 inverts the signal from level input C. In operation, an event arriving at input A passes through both XOR gates, presenting an event to both waiton gates. Depending on the level of level input C, only one waiton gate passes the event to output B1 or B0.
To operate properly, selector circuit 200 must reset the state pending at the input to the unused waiton gate, the waiton gate not enabled to pass the event to a corresponding output. Otherwise, an event received at input A could pass to both outputs of selector circuit 200. Each event received at input A should only pass to one output, not both.
To reset the state at the input of the unused waiton gate, selector circuit 200 includes a cross-connection from the outputs of waiton gates 230 and 240 to the inputs of XOR gates 210 and 220. Consequently, the input to the unused waiton gate is changed twice for each event received at input A, once when the event from input A passes through the XOR gate connected to that gate and again when the output of the active waiton gate passes its output event through that same XOR gate. For instance, assume an event at input A passes through XOR gates 210 and 220 to the inputs of waiton gates 230 and 240, respectively. Assuming C is true, the event passes from the output of waiton gate 230 to output B1. The event passed through waiton gate 230 also causes XOR gate 220 to reset the input of waiton gate 240.
Selector circuit 200 is not the only circuit used in asynchronous systems to steer events. For example, a decision wait circuit can also be used in asynchronous systems using transition encoding of events. As shown in FIG. 3, the decision wait circuit includes two event inputs A0 and A1, two event outputs B0 and B1, and a third event input C. The decision wait circuit must be allowed to respond to an event at input A0 before applying an event at input A0 or A1 again or to an event at input A1 before applying an event at input A0 or A1 again. The decision wait circuit produces an event on output B1 in response to the later arriving of events at inputs C and A1, and produces an event on output B0 in response to the later arriving of events at inputs C and A0.
FIG. 4 shows a logic diagram for a decision wait circuit 400. Circuit 400 includes two XOR gates, 410 and 420, and two Muller C-elements, 430 and 440. When an event arrives at input C, XOR gates 410 and 420 pass the event into the inner inputs of Muller C-elements 430 and 440, respectively. A Muller C-element fires, i.e., changes its output from high to low or low to high, when both of its inputs receive an event. With the circuit connected as shown, an event at input C would appear at inputs of Muller C-elements 430 and 440. When both Muller C-elements receive the event at input C, Muller C-element 430 fires if it also receives an event from input A1, and Muller C-element 440 fires if it also receives an event from input A0.
Like selector circuit 200, decision wait circuit 400 must reset the state at the input of the unused Muller C-element. To reset the input, decision wait circuit 400 also includes a cross connection from the event outputs to the inputs of the XOR gates. As a result, the input to the unused Muller C-element is set twice, once when the event from input C passes through the XOR gate connected to the unused Muller C-element, and again when the output of the active Muller C-element passes the output event through that same XOR gate. For instance, assuming an event at input C passes through XOR gates 410 and 420 to the inputs of Muller C-elements 430 and 440, respectively, and assuming input A1 receives an event, Muller C-element 430 will fire. XOR gate 420, coupled at an input to the output of Muller C-element 430, again passes an event to Muller C-element 440 to remove the erroneous event.
Both selector circuit 200 and decision wait circuit 400 use a pair of XOR gates, which conventionally require eight transistors. For example, FIG. 5 shows a conventional XOR gate including eight transistors 510, 520, 530, 540, 550, 560, 570, and 580. This large number of transistors contributes to higher costs and greater space requirements on a chip. In addition, conventional XOR gates often generate substantial delays. Therefore, to reduce cost and improve performance, the XOR gates in the selector and decision wait circuits should include fewer transistors and lower delays.